#ifndef PANIC_H
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#define PANIC_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#define PANIC_RSN_NONE 0
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#define PANIC_RSN_DEBUGEXCEPTION 1
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#define PANIC_RSN_DOUBLEEXCEPTION 2
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#define PANIC_RSN_KERNELEXCEPTION 3
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#define PANIC_RSN_COPROCEXCEPTION 4
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#define PANIC_RSN_INTWDT_CPU0 5
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#define PANIC_RSN_INTWDT_CPU1 6
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#define PANIC_RSN_CACHEERR 7
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#define PANIC_RSN_MAX 7
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#ifndef __ASSEMBLER__
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#include "esp_err.h"
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/**
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* @brief If an OCD is connected over JTAG. set breakpoint 0 to the given function
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* address. Do nothing otherwise.
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* @param data Pointer to the target breakpoint position
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*/
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void esp_set_breakpoint_if_jtag(void *fn);
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#define ESP_WATCHPOINT_LOAD 0x40000000
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#define ESP_WATCHPOINT_STORE 0x80000000
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#define ESP_WATCHPOINT_ACCESS 0xC0000000
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/**
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* @brief Set a watchpoint to break/panic when a certain memory range is accessed.
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*
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* @param no Watchpoint number. On the ESP32, this can be 0 or 1.
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* @param adr Base address to watch
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* @param size Size of the region, starting at the base address, to watch. Must
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* be one of 2^n, with n in [0..6].
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* @param flags One of ESP_WATCHPOINT_* flags
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*
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* @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise
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*
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* @warning The ESP32 watchpoint hardware watches a region of bytes by effectively
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* masking away the lower n bits for a region with size 2^n. If adr does
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* not have zero for these lower n bits, you may not be watching the
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* region you intended.
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*/
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esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags);
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/**
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* @brief Clear a watchpoint
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*
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* @param no Watchpoint to clear
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*
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*/
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void esp_clear_watchpoint(int no);
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/**
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* @brief Checks stack pointer
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*/
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static inline bool esp_stack_ptr_is_sane(uint32_t sp)
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{
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return !(sp < 0x3ffae010UL || sp > 0x3ffffff0UL || ((sp & 0xf) != 0));
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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