/* xdm-regs.h - Common register and related definitions for the XDM
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(Xtensa Debug Module) */
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/* Copyright (c) 2011-2012 Tensilica Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#ifndef _XDM_REGS_H_
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#define _XDM_REGS_H_
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/* NOTE: This header file is included by C, assembler, and other sources.
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So any C-specific or asm-specific content must be appropriately #ifdef'd. */
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/*
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* XDM registers can be accessed using APB, ERI, or JTAG (via NAR).
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* Address offsets for APB and ERI are the same, and for JTAG
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* is different (due to the limited 7-bit NAR addressing).
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*
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* Here, we first provide the constants as APB / ERI address offsets.
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* This is necessary for assembler code (which accesses XDM via ERI),
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* because complex conversion macros between the two address maps
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* don't work in the assembler.
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* Conversion macros are used to convert these to/from JTAG (NAR),
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* addresses, for software using JTAG.
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*/
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/* FIXME: maybe provide only MISC+CS registers here, and leave specific
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subsystem registers in separate headers? eg. for TRAX, PERF, OCD */
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/* XDM_.... ERI addr [NAR addr] Description...... */
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/* TRAX */
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#define XDM_TRAX_ID 0x0000 /*[0x00] ID */
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#define XDM_TRAX_CONTROL 0x0004 /*[0x01] Control */
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#define XDM_TRAX_STATUS 0x0008 /*[0x02] Status */
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#define XDM_TRAX_DATA 0x000C /*[0x03] Data */
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#define XDM_TRAX_ADDRESS 0x0010 /*[0x04] Address */
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#define XDM_TRAX_TRIGGER 0x0014 /*[0x05] Stop PC */
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#define XDM_TRAX_MATCH 0x0018 /*[0x06] Stop PC Range */
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#define XDM_TRAX_DELAY 0x001C /*[0x07] Post Stop Trigger Capture Size */
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#define XDM_TRAX_STARTADDR 0x0020 /*[0x08] Trace Memory Start */
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#define XDM_TRAX_ENDADDR 0x0024 /*[0x09] Trace Memory End */
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#define XDM_TRAX_DEBUGPC 0x003C /*[0x0F] Debug PC */
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#define XDM_TRAX_P4CHANGE 0x0040 /*[0x10] X */
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#define XDM_TRAX_TIME0 0x0040 /*[0x10] First Time Register */
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#define XDM_TRAX_P4REV 0x0044 /*[0x11] X */
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#define XDM_TRAX_TIME1 0x0044 /*[0x11] Second Time Register */
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#define XDM_TRAX_P4DATE 0x0048 /*[0x12] X */
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#define XDM_TRAX_INTTIME_MAX 0x0048 /*[0x12] maximal Value of Timestamp IntTime */
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#define XDM_TRAX_P4TIME 0x004C /*[0x13] X */
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#define XDM_TRAX_PDSTATUS 0x0050 /*[0x14] Sample of PDebugStatus */
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#define XDM_TRAX_PDDATA 0x0054 /*[0x15] Sample of PDebugData */
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#define XDM_TRAX_STOP_PC 0x0058 /*[0x16] X */
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#define XDM_TRAX_STOP_ICNT 0x005C /*[0x16] X */
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#define XDM_TRAX_MSG_STATUS 0x0060 /*[0x17] X */
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#define XDM_TRAX_FSM_STATUS 0x0064 /*[0x18] X */
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#define XDM_TRAX_IB_STATUS 0x0068 /*[0x19] X */
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#define XDM_TRAX_STOPCNT 0x006C /*[0x1A] X */
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/* Performance Monitoring Counters */
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#define XDM_PERF_PMG 0x1000 /*[0x20] perf. mon. global control register */
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#define XDM_PERF_INTPC 0x1010 /*[0x24] perf. mon. interrupt PC */
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#define XDM_PERF_PM0 0x1080 /*[0x28] perf. mon. counter 0 value */
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#define XDM_PERF_PM1 0x1084 /*[0x29] perf. mon. counter 1 value */
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#define XDM_PERF_PM2 0x1088 /*[0x2A] perf. mon. counter 2 value */
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#define XDM_PERF_PM3 0x108C /*[0x2B] perf. mon. counter 3 value */
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#define XDM_PERF_PM4 0x1090 /*[0x2C] perf. mon. counter 4 value */
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#define XDM_PERF_PM5 0x1094 /*[0x2D] perf. mon. counter 5 value */
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#define XDM_PERF_PM6 0x1098 /*[0x2E] perf. mon. counter 6 value */
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#define XDM_PERF_PM7 0x109C /*[0x2F] perf. mon. counter 7 value */
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#define XDM_PERF_PM(n) (0x1080+((n)<<2)) /* perfmon cnt n=0..7 value */
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#define XDM_PERF_PMCTRL0 0x1100 /*[0x30] perf. mon. counter 0 control */
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#define XDM_PERF_PMCTRL1 0x1104 /*[0x31] perf. mon. counter 1 control */
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#define XDM_PERF_PMCTRL2 0x1108 /*[0x32] perf. mon. counter 2 control */
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#define XDM_PERF_PMCTRL3 0x110C /*[0x33] perf. mon. counter 3 control */
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#define XDM_PERF_PMCTRL4 0x1110 /*[0x34] perf. mon. counter 4 control */
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#define XDM_PERF_PMCTRL5 0x1114 /*[0x35] perf. mon. counter 5 control */
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#define XDM_PERF_PMCTRL6 0x1118 /*[0x36] perf. mon. counter 6 control */
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#define XDM_PERF_PMCTRL7 0x111C /*[0x37] perf. mon. counter 7 control */
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#define XDM_PERF_PMCTRL(n) (0x1100+((n)<<2)) /* perfmon cnt n=0..7 control */
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#define XDM_PERF_PMSTAT0 0x1180 /*[0x38] perf. mon. counter 0 status */
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#define XDM_PERF_PMSTAT1 0x1184 /*[0x39] perf. mon. counter 1 status */
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#define XDM_PERF_PMSTAT2 0x1188 /*[0x3A] perf. mon. counter 2 status */
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#define XDM_PERF_PMSTAT3 0x118C /*[0x3B] perf. mon. counter 3 status */
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#define XDM_PERF_PMSTAT4 0x1190 /*[0x3C] perf. mon. counter 4 status */
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#define XDM_PERF_PMSTAT5 0x1194 /*[0x3D] perf. mon. counter 5 status */
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#define XDM_PERF_PMSTAT6 0x1198 /*[0x3E] perf. mon. counter 6 status */
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#define XDM_PERF_PMSTAT7 0x119C /*[0x3F] perf. mon. counter 7 status */
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#define XDM_PERF_PMSTAT(n) (0x1180+((n)<<2)) /* perfmon cnt n=0..7 status */
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/* On-Chip-Debug (OCD) */
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#define XDM_OCD_ID 0x2000 /*[0x40] ID register */
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#define XDM_OCD_DCR_CLR 0x2008 /*[0x42] Debug Control reg clear */
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#define XDM_OCD_DCR_SET 0x200C /*[0x43] Debug Control reg set */
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#define XDM_OCD_DSR 0x2010 /*[0x44] Debug Status reg */
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#define XDM_OCD_DDR 0x2014 /*[0x45] Debug Data reg */
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#define XDM_OCD_DDREXEC 0x2018 /*[0x46] Debug Data reg + execute-DIR */
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#define XDM_OCD_DIR0EXEC 0x201C /*[0x47] Debug Instruction reg, word 0 + execute-DIR */
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#define XDM_OCD_DIR0 0x2020 /*[0x48] Debug Instruction reg, word 1 */
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#define XDM_OCD_DIR1 0x2024 /*[0x49] Debug Instruction reg, word 2 */
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#define XDM_OCD_DIR2 0x2028 /*[0x4A] Debug Instruction reg, word 3 */
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#define XDM_OCD_DIR3 0x202C /*[0x49] Debug Instruction reg, word 4 */
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#define XDM_OCD_DIR4 0x2030 /*[0x4C] Debug Instruction reg, word 5 */
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#define XDM_OCD_DIR5 0x2034 /*[0x4D] Debug Instruction reg, word 5 */
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#define XDM_OCD_DIR6 0x2038 /*[0x4E] Debug Instruction reg, word 6 */
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#define XDM_OCD_DIR7 0x203C /*[0x4F] Debug Instruction reg, word 7 */
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/* Miscellaneous Registers */
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#define XDM_MISC_PWRCTL 0x3020 /*[0x58] Power and Reset Control */
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#define XDM_MISC_PWRSTAT 0x3024 /*[0x59] Power and Reset Status */
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#define XDM_MISC_ERISTAT 0x3028 /*[0x5A] ERI Transaction Status */
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#define XDM_MISC_DATETIME 0x3034 /*[0x5D] [INTERNAL] Timestamps of build */
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#define XDM_MISC_UBID 0x3038 /*[0x5E] [INTERNAL] Build Unique ID */
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#define XDM_MISC_CID 0x303C /*[0x5F] [INTERNAL] Customer ID */
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/* CoreSight compatibility */
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#define XDM_CS_ITCTRL 0x3F00 /*[0x60] InTegration Mode control reg */
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#define XDM_CS_CLAIMSET 0x3FA0 /*[0x68] Claim Tag Set reg */
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#define XDM_CS_CLAIMCLR 0x3FA4 /*[0x69] Claim Tag Clear reg */
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#define XDM_CS_LOCK_ACCESS 0x3FB0 /*[0x6B] Lock Access (writing 0xC5ACCE55 unlocks) */
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#define XDM_CS_LOCK_STATUS 0x3FB4 /*[0x6D] Lock Status */
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#define XDM_CS_AUTH_STATUS 0x3FB8 /*[0x6E] Authentication Status */
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#define XDM_CS_DEV_ID 0x3FC8 /*[0x72] Device ID */
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#define XDM_CS_DEV_TYPE 0x3FCC /*[0x73] Device Type */
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#define XDM_CS_PER_ID4 0x3FD0 /*[0x74] Peripheral ID reg byte 4 */
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#define XDM_CS_PER_ID5 0x3FD4 /*[0x75] Peripheral ID reg byte 5 */
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#define XDM_CS_PER_ID6 0x3FD8 /*[0x76] Peripheral ID reg byte 6 */
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#define XDM_CS_PER_ID7 0x3FDC /*[0x77] Peripheral ID reg byte 7 */
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#define XDM_CS_PER_ID0 0x3FE0 /*[0x78] Peripheral ID reg byte 0 */
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#define XDM_CS_PER_ID1 0x3FE4 /*[0x79] Peripheral ID reg byte 1 */
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#define XDM_CS_PER_ID2 0x3FE8 /*[0x7A] Peripheral ID reg byte 2 */
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#define XDM_CS_PER_ID3 0x3FEC /*[0x7B] Peripheral ID reg byte 3 */
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#define XDM_CS_COMP_ID0 0x3FF0 /*[0x7C] Component ID reg byte 0 */
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#define XDM_CS_COMP_ID1 0x3FF4 /*[0x7D] Component ID reg byte 1 */
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#define XDM_CS_COMP_ID2 0x3FF8 /*[0x7E] Component ID reg byte 2 */
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#define XDM_CS_COMP_ID3 0x3FFC /*[0x7F] Component ID reg byte 3 */
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#define CS_PER_ID0 0x00000003
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#define CS_PER_ID1 0x00000021
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#define CS_PER_ID2 0x0000000f
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#define CS_PER_ID3 0x00000000
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#define CS_PER_ID4 0x00000024
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#define CS_COMP_ID0 0x0000000d
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#define CS_COMP_ID1 0x00000090
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#define CS_COMP_ID2 0x00000005
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#define CS_COMP_ID3 0x000000b1
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#define CS_DEV_TYPE 0x00000015
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#define XTENSA_IDCODE 0x120034e5 // FIXME (upper bits not spec. out but BE is !)
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#define XTENSA_MFC_ID (XTENSA_IDCODE & 0xFFF)
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#define CS_DEV_ID XTENSA_IDCODE
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#define NXS_OCD_REG(val) ((val >= 0x40) && (val <= 0x5F))
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#define NXS_TRAX_REG(val) val <= 0x3F
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#define ERI_TRAX_REG(val) ((val & 0xFFFF) < 0x1000)
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#define ERI_OCD_REG(val) ((val & 0xFFFF) >= 0x2000) && ((val & 0xFFFF) < 0x4000))
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/* Convert above 14-bit ERI/APB address/offset to 7-bit NAR address: */
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#define _XDM_ERI_TO_NAR(a) ( ((a)&0x3F80)==0x0000 ? (((a)>>2) & 0x1F) \
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: ((a)&0x3E00)==0x1000 ? (0x20 | (((a)>>2) & 7) | (((a)>>4) & 0x18)) \
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: ((a)&0x3FC0)==0x2000 ? (0x40 | (((a)>>2) & 0xF)) \
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: ((a)&0x3FE0)==0x3020 ? (0x50 | (((a)>>2) & 0xF)) \
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: ((a)&0x3FFC)==0x3F00 ? 0x60 \
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: ((a)&0x3F80)==0x3F80 ? (0x60 | (((a)>>2) & 0x1F)) \
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: -1 )
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#define XDM_ERI_TO_NAR(a) _XDM_ERI_TO_NAR(a & 0xFFFF)
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/* Convert 7-bit NAR address back to ERI/APB address/offset: */
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#define _XDM_NAR_TO_APB(a) ((a) <= 0x1f ? ((a) << 2) \
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:(a) >= 0x20 && (a) <= 0x3F ? (0x1000 | (((a)& 7) << 2) | (((a)&0x18)<<4)) \
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:(a) >= 0x40 && (a) <= 0x4F ? (0x2000 | (((a)&0xF) << 2)) \
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:(a) >= 0x58 && (a) <= 0x5F ? (0x3000 | (((a)&0xF) << 2)) \
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:(a) == 0x60 ? (0x3F00) \
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:(a) >= 0x68 && (a) <= 0x7F ? (0x3F80 | (((a)&0x1F) << 2)) \
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: -1)
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#define XDM_NAR_TO_APB(a) _XDM_NAR_TO_APB((a & 0xFFFF))
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#define XDM_NAR_TO_ERI(a) _XDM_NAR_TO_APB((a & 0xFFFF)) | 0x000000
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/* Convert APB to ERI address */
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#define XDM_APB_TO_ERI(a) ((a) | (0x100000))
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#define XDM_ERI_TO_APB(a) ((a) & (0x0FFFFF))
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/*********** Bit definitions within some of the above registers ***********/
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#define OCD_ID_LSDDRP 0x01000000
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#define OCD_ID_LSDDRP_SHIFT 24
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#define OCD_ID_ENDIANESS 0x00000001
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#define OCD_ID_ENDIANESS_SHIFT 0
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#define OCD_ID_PSO 0x0000000C
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#define OCD_ID_PSO_SHIFT 2
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#define OCD_ID_TRACEPORT 0x00000080
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#define OCD_ID_TRACEPORT_SHIFT 7
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/* Power Status register. NOTE: different bit positions in JTAG vs. ERI/APB !! */
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/* ERI/APB: */
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#define PWRSTAT_CORE_DOMAIN_ON 0x00000001 /* set if core is powered on */
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#define PWRSTAT_CORE_DOMAIN_ON_SHIFT 0
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#define PWRSTAT_WAKEUP_RESET 0x00000002 /* [ERI only] 0=cold start, 1=PSO wakeup */
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#define PWRSTAT_WAKEUP_RESET_SHIFT 1
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#define PWRSTAT_CACHES_LOST_POWER 0x00000004 /* [ERI only] set if caches (/localmems?) lost power */
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/* FIXME: does this include local memories? */
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#define PWRSTAT_CACHES_LOST_POWER_SHIFT 2
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#define PWRSTAT_CORE_STILL_NEEDED 0x00000010 /* set if others keeping core awake */
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#define PWRSTAT_CORE_STILL_NEEDED_SHIFT 4
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#define PWRSTAT_MEM_DOMAIN_ON 0x00000100 /* set if memory domain is powered on */
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#define PWRSTAT_MEM_DOMAIN_ON_SHIFT 8
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#define PWRSTAT_DEBUG_DOMAIN_ON 0x00001000 /* set if debug domain is powered on */
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#define PWRSTAT_DEBUG_DOMAIN_ON_SHIFT 12
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#define PWRSTAT_ALL_ON PWRSTAT_CORE_DOMAIN_ON | PWRSTAT_MEM_DOMAIN_ON | PWRSTAT_DEBUG_DOMAIN_ON
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#define PWRSTAT_CORE_WAS_RESET 0x00010000 /* [APB only] set if core got reset */
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#define PWRSTAT_CORE_WAS_RESET_SHIFT 16
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#define PWRSTAT_DEBUG_WAS_RESET 0x10000000 /* set if debug module got reset */
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#define PWRSTAT_DEBUG_WAS_RESET_SHIFT 28
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/* JTAG: */
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#define J_PWRSTAT_CORE_DOMAIN_ON 0x01 /* set if core is powered on */
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#define J_PWRSTAT_MEM_DOMAIN_ON 0x02 /* set if memory domain is powered on */
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#define J_PWRSTAT_DEBUG_DOMAIN_ON 0x04 /* set if debug domain is powered on */
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#define J_PWRSTAT_ALL_ON J_PWRSTAT_CORE_DOMAIN_ON | J_PWRSTAT_MEM_DOMAIN_ON | J_PWRSTAT_DEBUG_DOMAIN_ON
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#define J_PWRSTAT_CORE_STILL_NEEDED 0x08 /* set if others keeping core awake */
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#define J_PWRSTAT_CORE_WAS_RESET 0x10 /* set if core got reset */
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#define J_PWRSTAT_DEBUG_WAS_RESET 0x40 /* set if debug module got reset */
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/* Power Control register. NOTE: different bit positions in JTAG vs. ERI/APB !! */
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/* ERI/APB: */
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#define PWRCTL_CORE_SHUTOFF 0x00000001 /* [ERI only] core wants to shut off on WAITI */
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#define PWRCTL_CORE_SHUTOFF_SHIFT 0
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#define PWRCTL_CORE_WAKEUP 0x00000001 /* [APB only] set to force core to stay powered on */
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#define PWRCTL_CORE_WAKEUP_SHIFT 0
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#define PWRCTL_MEM_WAKEUP 0x00000100 /* set to force memory domain to stay powered on */
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#define PWRCTL_MEM_WAKEUP_SHIFT 8
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#define PWRCTL_DEBUG_WAKEUP 0x00001000 /* set to force debug domain to stay powered on */
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#define PWRCTL_DEBUG_WAKEUP_SHIFT 12
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#define PWRCTL_ALL_ON PWRCTL_CORE_WAKEUP | PWRCTL_MEM_WAKEUP | PWRCTL_DEBUG_WAKEUP
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#define PWRCTL_CORE_RESET 0x00010000 /* [APB only] set to assert core reset */
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#define PWRCTL_CORE_RESET_SHIFT 16
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#define PWRCTL_DEBUG_RESET 0x10000000 /* set to assert debug module reset */
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#define PWRCTL_DEBUG_RESET_SHIFT 28
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/* JTAG: */
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#define J_PWRCTL_CORE_WAKEUP 0x01 /* set to force core to stay powered on */
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#define J_PWRCTL_MEM_WAKEUP 0x02 /* set to force memory domain to stay powered on */
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#define J_PWRCTL_DEBUG_WAKEUP 0x04 /* set to force debug domain to stay powered on */
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#define J_DEBUG_USE 0x80 /* */
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#define J_PWRCTL_ALL_ON J_DEBUG_USE | J_PWRCTL_CORE_WAKEUP | J_PWRCTL_MEM_WAKEUP | J_PWRCTL_DEBUG_WAKEUP
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#define J_PWRCTL_DEBUG_ON J_DEBUG_USE | J_PWRCTL_DEBUG_WAKEUP
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#define J_PWRCTL_CORE_RESET 0x10 /* set to assert core reset */
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#define J_PWRCTL_DEBUG_RESET 0x40 /* set to assert debug module reset */
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#define J_PWRCTL_WRITE_MASK 0xFF
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#define J_PWRSTAT_WRITE_MASK 0xFF
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#define PWRCTL_WRITE_MASK ~0
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#define PWRSTAT_WRITE_MASK ~0
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/************ The following are only relevant for JTAG, so perhaps belong in OCD only **************/
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/* XDM 5-bit JTAG Instruction Register (IR) values: */
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#define XDM_IR_PWRCTL 0x08 /* select 8-bit Power/Reset Control (PRC) */
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#define XDM_IR_PWRSTAT 0x09 /* select 8-bit Power/Reset Status (PRS) */
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#define XDM_IR_NAR_SEL 0x1c /* select altern. 8-bit NAR / 32-bit NDR (Nexus-style) */
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#define XDM_IR_NDR_SEL 0x1d /* select altern. 32-bit NDR / 8-bit NAR
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(FIXME - functionality not yet in HW) */
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#define XDM_IR_IDCODE 0x1e /* select 32-bit JTAG IDCODE */
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#define XDM_IR_BYPASS 0x1f /* select 1-bit bypass */
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#define XDM_IR_WIDTH 5 /* width of IR for Xtensa TAP */
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/* NAR register bits: */
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#define XDM_NAR_WRITE 0x01
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#define XDM_NAR_ADDR_MASK 0xFE
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#define XDM_NAR_ADDR_SHIFT 1
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#define XDM_NAR_BUSY 0x02
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#define XDM_NAR_ERROR 0x01
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#define NEXUS_DIR_READ 0x00
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#define NEXUS_DIR_WRITE 0x01
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/************ Define DCR register bits **************/
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#define DCR_ENABLEOCD 0x0000001
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#define DCR_ENABLEOCD_SHIFT 0
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#define DCR_DEBUG_INT 0x0000002
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#define DCR_DEBUG_INT_SHIFT 1
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#define DCR_DEBUG_OVERRIDE 0x0000004
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#define DCR_DEBUG_OVERRIDE_SHIFT 2
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#define DCR_DEBUG_INTERCEPT 0x0000008
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#define DCR_DEBUG_INTERCEPT_SHIFT 3
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#define DCR_MASK_NMI 0x0000020
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#define DCR_MASK_NMI_SHIFT 5
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#define DCR_STEP_ENABLE 0x0000040
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#define DCR_STEP_ENABLE_SHIFT 6
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#define DCR_BREAK_IN_EN 0x0010000
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#define DCR_BREAK_IN_EN_SHIFT 16
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#define DCR_BREAK_OUT_EN 0x0020000
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#define DCR_BREAK_OUT_EN_SHIFT 17
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#define DCR_DEBUG_INT_EN 0x0040000
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#define DCR_DEBUG_INT_EN_SHIFT 18
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#define DCR_DBG_SW_ACTIVE 0x0100000
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#define DCR_DBG_SW_ACTIVE_SHIFT 20
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#define DCR_STALL_IN_EN 0x0200000
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#define DCR_STALL_IN_EN_SHIFT 21
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#define DCR_DEBUG_OUT_EN 0x0400000
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#define DCR_DEBUG_OUT_EN_SHIFT 22
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#define DCR_BREAK_OUT_ITO 0x1000000
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#define DCR_STALL_OUT_ITO 0x2000000
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#define DCR_STALL_OUT_ITO_SHIFT 25
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/************ Define DSR register bits **************/
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#define DOSR_EXECDONE_ER 0x01
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#define DOSR_EXECDONE_SHIFT 0
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#define DOSR_EXCEPTION_ER 0x02
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#define DOSR_EXCEPTION_SHIFT 1
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#define DOSR_BUSY 0x04
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#define DOSR_BUSY_SHIFT 2
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#define DOSR_OVERRUN 0x08
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#define DOSR_OVERRUN_SHIFT 3
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#define DOSR_INOCDMODE_ER 0x10
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#define DOSR_INOCDMODE_SHIFT 4
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#define DOSR_CORE_WROTE_DDR_ER 0x400
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#define DOSR_CORE_WROTE_DDR_SHIFT 10
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#define DOSR_CORE_READ_DDR_ER 0x800
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#define DOSR_CORE_READ_DDR_SHIFT 11
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#define DOSR_HOST_WROTE_DDR_ER 0x4000
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#define DOSR_HOST_WROTE_DDR_SHIFT 14
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#define DOSR_HOST_READ_DDR_ER 0x8000
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#define DOSR_HOST_READ_DDR_SHIFT 15
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#define DOSR_DEBUG_PEND_BIN 0x10000
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#define DOSR_DEBUG_PEND_HOST 0x20000
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#define DOSR_DEBUG_PEND_TRAX 0x40000
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#define DOSR_DEBUG_BIN 0x100000
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#define DOSR_DEBUG_HOST 0x200000
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#define DOSR_DEBUG_TRAX 0x400000
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#define DOSR_DEBUG_PEND_BIN_SHIFT 16
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#define DOSR_DEBUG_PEND_HOST_SHIFT 17
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#define DOSR_DEBUG_PEND_TRAX_SHIFT 18
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#define DOSR_DEBUG_BREAKIN 0x0100000
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#define DOSR_DEBUG_BREAKIN_SHIFT 20
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#define DOSR_DEBUG_HOST_SHIFT 21
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#define DOSR_DEBUG_TRAX_SHIFT 22
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#define DOSR_DEBUG_STALL 0x1000000
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#define DOSR_DEBUG_STALL_SHIFT 24
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#define DOSR_CORE_ON 0x40000000
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#define DOSR_CORE_ON_SHIFT 30
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#define DOSR_DEBUG_ON 0x80000000
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#define DOSR_DEBUG_ON_SHIFT 31
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/********** Performance monitor registers bits **********/
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#define PERF_PMG_ENABLE 0x00000001 /* global enable bit */
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#define PERF_PMG_ENABLE_SHIFT 0
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#define PERF_PMCTRL_INT_ENABLE 0x00000001 /* assert interrupt on overflow */
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#define PERF_PMCTRL_INT_ENABLE_SHIFT 0
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#define PERF_PMCTRL_KRNLCNT 0x00000008 /* ignore TRACELEVEL */
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#define PERF_PMCTRL_KRNLCNT_SHIFT 3
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#define PERF_PMCTRL_TRACELEVEL 0x000000F0 /* count when CINTLEVEL <= TRACELEVEL */
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#define PERF_PMCTRL_TRACELEVEL_SHIFT 4
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#define PERF_PMCTRL_SELECT 0x00001F00 /* events group selector */
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#define PERF_PMCTRL_SELECT_SHIFT 8
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#define PERF_PMCTRL_MASK 0xFFFF0000 /* events mask */
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#define PERF_PMCTRL_MASK_SHIFT 16
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#define PERF_PMSTAT_OVERFLOW 0x00000001 /* counter overflowed */
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#define PERF_PMSTAT_OVERFLOW_SHIFT 0
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#define PERF_PMSTAT_INT 0x00000010 /* interrupt asserted */
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#define PERF_PMSTAT_INT_SHIFT 4
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#if defined (USE_XDM_REGNAME) || defined (USE_DAP_REGNAME)
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/* Describes XDM register: */
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typedef struct {
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int reg;
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char* name;
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} regdef_t;
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/*char* regname(regdef_t* list, int regno)
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{
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unsigned i;
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for(i = 0 ; i < (sizeof(list) / sizeof(regdef_t)); i++){
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if(list[i].reg == regno)
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return list[i].name;
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}
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return "???";
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}*/
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/*
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* Returns the name of the specified XDM register number,
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* or simply "???" if the register number is not recognized.
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* FIXME - requires -1 as the last entry - change to compare the name to ???
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* or even better, make the code above to work.
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*/
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static char * regname(regdef_t* list, int reg)
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{
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int i = 0;
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while (list[i].reg != -1){
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if (list[i].reg == reg)
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break;
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i++;
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}
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return list[i].name;
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}
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#if defined (USE_XDM_REGNAME)
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regdef_t xdm_reglist[] =
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{
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{XDM_TRAX_ID ,"TRAX_ID" },
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{XDM_TRAX_CONTROL ,"CONTROL" },
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{XDM_TRAX_STATUS ,"STATUS" },
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{XDM_TRAX_DATA ,"DATA" },
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{XDM_TRAX_ADDRESS ,"ADDRESS" },
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{XDM_TRAX_TRIGGER ,"TRIGGER PC" },
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{XDM_TRAX_MATCH ,"PC MATCH" },
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{XDM_TRAX_DELAY ,"DELAY CNT." },
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{XDM_TRAX_STARTADDR ,"START ADDRESS"},
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{XDM_TRAX_ENDADDR ,"END ADDRESS" },
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{XDM_TRAX_DEBUGPC ,"DEBUG PC" },
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{XDM_TRAX_P4CHANGE ,"P4 CHANGE" },
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{XDM_TRAX_P4REV ,"P4 REV." },
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{XDM_TRAX_P4DATE ,"P4 DATE" },
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{XDM_TRAX_P4TIME ,"P4 TIME" },
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{XDM_TRAX_PDSTATUS ,"PD STATUS" },
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{XDM_TRAX_PDDATA ,"PD DATA" },
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{XDM_TRAX_STOP_PC ,"STOP PC" },
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{XDM_TRAX_STOP_ICNT ,"STOP ICNT" },
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{XDM_TRAX_MSG_STATUS ,"MSG STAT." },
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{XDM_TRAX_FSM_STATUS ,"FSM STAT." },
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{XDM_TRAX_IB_STATUS ,"IB STAT." },
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{XDM_OCD_ID ,"OCD_ID" },
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{XDM_OCD_DCR_CLR ,"DCR_CLR" },
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{XDM_OCD_DCR_SET ,"DCR_SET" },
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{XDM_OCD_DSR ,"DOSR" },
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{XDM_OCD_DDR ,"DDR" },
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{XDM_OCD_DDREXEC ,"DDREXEC" },
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{XDM_OCD_DIR0EXEC ,"DIR0EXEC"},
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{XDM_OCD_DIR0 ,"DIR0" },
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{XDM_OCD_DIR1 ,"DIR1" },
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{XDM_OCD_DIR2 ,"DIR2" },
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{XDM_OCD_DIR3 ,"DIR3" },
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{XDM_OCD_DIR4 ,"DIR4" },
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{XDM_OCD_DIR5 ,"DIR5" },
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{XDM_OCD_DIR6 ,"DIR6" },
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{XDM_OCD_DIR7 ,"DIR7" },
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{XDM_PERF_PMG ,"PMG" },
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{XDM_PERF_INTPC ,"INTPC" },
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{XDM_PERF_PM0 ,"PM0 " },
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{XDM_PERF_PM1 ,"PM1 " },
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{XDM_PERF_PM2 ,"PM2 " },
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{XDM_PERF_PM3 ,"PM3 " },
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{XDM_PERF_PM4 ,"PM4 " },
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{XDM_PERF_PM5 ,"PM5 " },
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{XDM_PERF_PM6 ,"PM6 " },
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{XDM_PERF_PM7 ,"PM7 " },
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{XDM_PERF_PMCTRL0 ,"PMCTRL0"},
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{XDM_PERF_PMCTRL1 ,"PMCTRL1"},
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{XDM_PERF_PMCTRL2 ,"PMCTRL2"},
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{XDM_PERF_PMCTRL3 ,"PMCTRL3"},
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{XDM_PERF_PMCTRL4 ,"PMCTRL4"},
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{XDM_PERF_PMCTRL5 ,"PMCTRL5"},
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{XDM_PERF_PMCTRL6 ,"PMCTRL6"},
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{XDM_PERF_PMCTRL7 ,"PMCTRL7"},
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{XDM_PERF_PMSTAT0 ,"PMSTAT0"},
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{XDM_PERF_PMSTAT1 ,"PMSTAT1"},
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{XDM_PERF_PMSTAT2 ,"PMSTAT2"},
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{XDM_PERF_PMSTAT3 ,"PMSTAT3"},
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{XDM_PERF_PMSTAT4 ,"PMSTAT4"},
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{XDM_PERF_PMSTAT5 ,"PMSTAT5"},
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{XDM_PERF_PMSTAT6 ,"PMSTAT6"},
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{XDM_PERF_PMSTAT7 ,"PMSTAT7"},
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{XDM_MISC_PWRCTL ,"PWRCTL" },
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{XDM_MISC_PWRSTAT ,"PWRSTAT" },
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{XDM_MISC_ERISTAT ,"ERISTAT" },
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{XDM_MISC_DATETIME ,"DATETIME"},
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{XDM_MISC_UBID ,"UBID" },
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{XDM_MISC_CID ,"CID" },
|
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{XDM_CS_ITCTRL ,"ITCTRL" },
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{XDM_CS_CLAIMSET ,"CLAIMSET" },
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{XDM_CS_CLAIMCLR ,"CLAIMCLR" },
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{XDM_CS_LOCK_ACCESS ,"LOCK_ACCESS"},
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{XDM_CS_LOCK_STATUS ,"LOCK_STATUS"},
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{XDM_CS_AUTH_STATUS ,"AUTH_STATUS"},
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{XDM_CS_DEV_ID ,"DEV_ID" },
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{XDM_CS_DEV_TYPE ,"DEV_TYPE" },
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{XDM_CS_PER_ID4 ,"PER_ID4" },
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{XDM_CS_PER_ID5 ,"PER_ID5" },
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{XDM_CS_PER_ID6 ,"PER_ID6" },
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{XDM_CS_PER_ID7 ,"PER_ID7" },
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{XDM_CS_PER_ID0 ,"PER_ID0" },
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{XDM_CS_PER_ID1 ,"PER_ID1" },
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{XDM_CS_PER_ID2 ,"PER_ID2" },
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{XDM_CS_PER_ID3 ,"PER_ID3" },
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{XDM_CS_COMP_ID0 ,"COMP_ID0" },
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{XDM_CS_COMP_ID1 ,"COMP_ID1" },
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{XDM_CS_COMP_ID2 ,"COMP_ID2" },
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{XDM_CS_COMP_ID3 ,"COMP_ID3" },
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{-1 ,"???" },
|
};
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#endif
|
|
#endif
|
|
#endif /* _XDM_REGS_H_ */
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