/*
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* Customer ID=11656; Build=0x5f626; Copyright (c) 2012 by Tensilica Inc. ALL RIGHTS RESERVED.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef __XT_PERF_CONSTS_H__
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#define __XT_PERF_CONSTS_H__
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/*
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* Performance monitor counter selectors
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*/
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#define XTPERF_CNT_COMMITTED_INSN 0x8002 /* Instructions committed */
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#define XTPERF_CNT_BRANCH_PENALTY 0x8003 /* Branch penalty cycles */
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#define XTPERF_CNT_PIPELINE_INTERLOCKS 0x8004 /* Pipeline interlocks cycles */
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#define XTPERF_CNT_ICACHE_MISSES 0x8005 /* ICache misses penalty in cycles */
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#define XTPERF_CNT_DCACHE_MISSES 0x8006 /* DCache misses penalty in cycles */
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#define XTPERF_CNT_CYCLES 0 /* Count cycles */
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#define XTPERF_CNT_OVERFLOW 1 /* Overflow of counter n-1 (assuming this is counter n) */
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#define XTPERF_CNT_INSN 2 /* Successfully completed instructions */
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#define XTPERF_CNT_D_STALL 3 /* Data-related GlobalStall cycles */
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#define XTPERF_CNT_I_STALL 4 /* Instruction-related and other GlobalStall cycles */
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#define XTPERF_CNT_EXR 5 /* Exceptions and pipeline replays */
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#define XTPERF_CNT_BUBBLES 6 /* Hold and other bubble cycles */
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#define XTPERF_CNT_I_TLB 7 /* Instruction TLB Accesses (per instruction retiring) */
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#define XTPERF_CNT_I_MEM 8 /* Instruction memory accesses (per instruction retiring) */
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#define XTPERF_CNT_D_TLB 9 /* Data TLB accesses */
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#define XTPERF_CNT_D_LOAD_U1 10 /* Data memory load instruction (load-store unit 1) */
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#define XTPERF_CNT_D_STORE_U1 11 /* Data memory store instruction (load-store unit 1) */
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#define XTPERF_CNT_D_ACCESS_U1 12 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 1) */
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#define XTPERF_CNT_D_LOAD_U2 13 /* Data memory load instruction (load-store unit 2) */
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#define XTPERF_CNT_D_STORE_U2 14 /* Data memory store instruction (load-store unit 2) */
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#define XTPERF_CNT_D_ACCESS_U2 15 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 2) */
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#define XTPERF_CNT_D_LOAD_U3 16 /* Data memory load instruction (load-store unit 3) */
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#define XTPERF_CNT_D_STORE_U3 17 /* Data memory store instruction (load-store unit 3) */
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#define XTPERF_CNT_D_ACCESS_U3 18 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 3) */
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#define XTPERF_CNT_MULTIPLE_LS 22 /* Multiple Load/Store */
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#define XTPERF_CNT_OUTBOUND_PIF 23 /* Outbound PIF transactions */
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#define XTPERF_CNT_INBOUND_PIF 24 /* Inbound PIF transactions */
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#define XTPERF_CNT_PREFETCH 26 /* Prefetch events */
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/*
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* Masks for each of the selector listed above
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*/
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/* XTPERF_CNT_COMMITTED_INSN selector mask */
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#define XTPERF_MASK_COMMITTED_INSN 0x0001
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/* XTPERF_CNT_BRANCH_PENALTY selector mask */
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#define XTPERF_MASK_BRANCH_PENALTY 0x0001
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/* XTPERF_CNT_PIPELINE_INTERLOCKS selector mask */
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#define XTPERF_MASK_PIPELINE_INTERLOCKS 0x0001
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/* XTPERF_CNT_ICACHE_MISSES selector mask */
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#define XTPERF_MASK_ICACHE_MISSES 0x0001
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/* XTPERF_CNT_DCACHE_MISSES selector mask */
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#define XTPERF_MASK_DCACHE_MISSES 0x0001
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/* XTPERF_CNT_CYCLES selector mask */
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#define XTPERF_MASK_CYCLES 0x0001
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/* XTPERF_CNT_OVERFLOW selector mask */
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#define XTPERF_MASK_OVERFLOW 0x0001
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/*
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* XTPERF_CNT_INSN selector mask
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*/
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#define XTPERF_MASK_INSN_ALL 0x8DFF
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#define XTPERF_MASK_INSN_JX 0x0001 /* JX */
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#define XTPERF_MASK_INSN_CALLX 0x0002 /* CALLXn */
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#define XTPERF_MASK_INSN_RET 0x0004 /* call return i.e. RET, RETW */
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#define XTPERF_MASK_INSN_RF 0x0008 /* supervisor return i.e. RFDE, RFE, RFI, RFWO, RFWU */
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#define XTPERF_MASK_INSN_BRANCH_TAKEN 0x0010 /* Conditional branch taken, or loopgtz/loopnez skips loop */
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#define XTPERF_MASK_INSN_J 0x0020 /* J */
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#define XTPERF_MASK_INSN_CALL 0x0040 /* CALLn */
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#define XTPERF_MASK_INSN_BRANCH_NOT_TAKEN 0x0080 /* Conditional branch fall through (aka. not-taken branch) */
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#define XTPERF_MASK_INSN_LOOP_TAKEN 0x0100 /* Loop instr falls into loop (aka. taken loop) */
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#define XTPERF_MASK_INSN_LOOP_BEG 0x0400 /* Loopback taken to LBEG */
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#define XTPERF_MASK_INSN_LOOP_END 0x0800 /* Loopback falls through to LEND */
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#define XTPERF_MASK_INSN_NON_BRANCH 0x8000 /* Non-branch instruction (aka. non-CTI) */
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/*
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* XTPERF_CNT_D_STALL selector mask
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*/
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#define XTPERF_MASK_D_STALL_ALL 0x01FE
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#define XTPERF_MASK_D_STALL_STORE_BUF_FULL 0x0002 /* Store buffer full stall */
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#define XTPERF_MASK_D_STALL_STORE_BUF_CONFLICT 0x0004 /* Store buffer conflict stall */
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#define XTPERF_MASK_D_STALL_CACHE_MISS 0x0008 /* DCache-miss stall */
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#define XTPERF_MASK_D_STALL_BUSY 0x0010 /* Data RAM/ROM/XLMI busy stall */
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#define XTPERF_MASK_D_STALL_IN_PIF 0x0020 /* Data inbound-PIF request stall (incl s32c1i) */
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#define XTPERF_MASK_D_STALL_MHT_LOOKUP 0x0040 /* MHT lookup stall */
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#define XTPERF_MASK_D_STALL_UNCACHED_LOAD 0x0080 /* Uncached load stall (included in MHT lookup stall) */
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#define XTPERF_MASK_D_STALL_BANK_CONFLICT 0x0100 /* Bank-conflict stall */
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/*
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* XTPERF_CNT_I_STALL selector mask
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*/
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#define XTPERF_MASK_I_STALL_ALL 0x01FF
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#define XTPERF_MASK_I_STALL_CACHE_MISS 0x0001 /* ICache-miss stall */
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#define XTPERF_MASK_I_STALL_BUSY 0x0002 /* Instruction RAM/ROM busy stall */
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#define XTPERF_MASK_I_STALL_IN_PIF 0x0004 /* Instruction RAM inbound-PIF request stall */
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#define XTPERF_MASK_I_STALL_TIE_PORT 0x0008 /* TIE port stall */
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#define XTPERF_MASK_I_STALL_EXTERNAL_SIGNAL 0x0010 /* External RunStall signal status */
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#define XTPERF_MASK_I_STALL_UNCACHED_FETCH 0x0020 /* Uncached fetch stall */
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#define XTPERF_MASK_I_STALL_FAST_L32R 0x0040 /* FastL32R stall */
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#define XTPERF_MASK_I_STALL_ITERATIVE_MUL 0x0080 /* Iterative multiply stall */
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#define XTPERF_MASK_I_STALL_ITERATIVE_DIV 0x0100 /* Iterative divide stall */
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/*
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* XTPERF_CNT_EXR selector mask
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*/
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#define XTPERF_MASK_EXR_ALL 0x01FF
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#define XTPERF_MASK_EXR_REPLAYS 0x0001 /* Other Pipeline Replay (i.e. excludes $ miss etc.) */
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#define XTPERF_MASK_EXR_LEVEL1_INT 0x0002 /* Level-1 interrupt */
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#define XTPERF_MASK_EXR_LEVELH_INT 0x0004 /* Greater-than-level-1 interrupt */
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#define XTPERF_MASK_EXR_DEBUG 0x0008 /* Debug exception */
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#define XTPERF_MASK_EXR_NMI 0x0010 /* NMI */
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#define XTPERF_MASK_EXR_WINDOW 0x0020 /* Window exception */
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#define XTPERF_MASK_EXR_ALLOCA 0x0040 /* Alloca exception */
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#define XTPERF_MASK_EXR_OTHER 0x0080 /* Other exceptions */
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#define XTPERF_MASK_EXR_MEM_ERR 0x0100 /* HW-corrected memory error */
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/*
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* XTPERF_CNT_BUBBLES selector mask
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*/
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#define XTPERF_MASK_BUBBLES_ALL 0x01FD
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#define XTPERF_MASK_BUBBLES_PSO 0x0001 /* Processor domain PSO bubble */
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#define XTPERF_MASK_BUBBLES_R_HOLD_D_CACHE_MISS 0x0004 /* R hold caused by DCache miss */
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#define XTPERF_MASK_BUBBLES_R_HOLD_STORE_RELEASE 0x0008 /* R hold caused by Store release */
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#define XTPERF_MASK_BUBBLES_R_HOLD_REG_DEP 0x0010 /* R hold caused by register dependency */
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#define XTPERF_MASK_BUBBLES_R_HOLD_WAIT 0x0020 /* R hold caused by MEMW, EXTW or EXCW */
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#define XTPERF_MASK_BUBBLES_R_HOLD_HALT 0x0040 /* R hold caused by Halt instruction (TX only) */
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#define XTPERF_MASK_BUBBLES_CTI 0x0080 /* CTI bubble (e.g. branch delay slot) */
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#define XTPERF_MASK_BUBBLES_WAITI 0x0100 /* WAITI bubble */
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/*
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* XTPERF_CNT_I_TLB selector mask
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*/
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#define XTPERF_MASK_I_TLB_ALL 0x000F
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#define XTPERF_MASK_I_TLB_HITS 0x0001 /* Hit */
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#define XTPERF_MASK_I_TLB_REPLAYS 0x0002 /* Replay of instruction due to ITLB miss */
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#define XTPERF_MASK_I_TLB_REFILLS 0x0004 /* HW-assisted TLB Refill completes */
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#define XTPERF_MASK_I_TLB_MISSES 0x0008 /* ITLB Miss Exception */
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/*
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* XTPERF_CNT_I_MEM selector mask
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*/
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#define XTPERF_MASK_I_MEM_ALL 0x000F
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#define XTPERF_MASK_I_MEM_CACHE_HITS 0x0001 /* ICache Hit */
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#define XTPERF_MASK_I_MEM_CACHE_MISSES 0x0002 /* ICache Miss (includes uncached) */
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#define XTPERF_MASK_I_MEM_IRAM 0x0004 /* InstRAM or InstROM */
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#define XTPERF_MASK_I_MEM_BYPASS 0x0008 /* Bypass (i.e. uncached) fetch */
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/*
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* XTPERF_CNT_D_TLB selector mask
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*/
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#define XTPERF_MASK_D_TLB_ALL 0x000F
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#define XTPERF_MASK_D_TLB_HITS 0x0001 /* Hit */
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#define XTPERF_MASK_D_TLB_REPLAYS 0x0002 /* Replay of instruction due to DTLB miss */
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#define XTPERF_MASK_D_TLB_REFILLS 0x0004 /* HW-assisted TLB Refill completes */
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#define XTPERF_MASK_D_TLB_MISSES 0x0008 /* DTLB Miss Exception */
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/*
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* XTPERF_CNT_D_LOAD_U* selector mask
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*/
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#define XTPERF_MASK_D_LOAD_ALL 0x000F
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#define XTPERF_MASK_D_LOAD_CACHE_HITS 0x0001 /* Cache Hit */
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#define XTPERF_MASK_D_LOAD_CACHE_MISSES 0x0002 /* Cache Miss */
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#define XTPERF_MASK_D_LOAD_LOCAL_MEM 0x0004 /* Local memory hit */
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#define XTPERF_MASK_D_LOAD_BYPASS 0x0008 /* Bypass (i.e. uncached) load */
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/*
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* XTPERF_CNT_D_STORE_U* selector mask
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*/
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#define XTPERF_MASK_D_STORE_ALL 0x000F
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#define XTPERF_MASK_D_STORE_CACHE_HITS 0x0001 /* DCache Hit */
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#define XTPERF_MASK_D_STORE_CACHE_MISSES 0x0002 /* DCache Miss */
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#define XTPERF_MASK_D_STORE_LOCAL_MEM 0x0004 /* Local memory hit */
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#define XTPERF_MASK_D_STORE_PIF 0x0008 /* PIF Store */
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/*
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* XTPERF_CNT_D_ACCESS_U* selector mask
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*/
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#define XTPERF_MASK_D_ACCESS_ALL 0x000F
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#define XTPERF_MASK_D_ACCESS_CACHE_MISSES 0x0001 /* DCache Miss */
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#define XTPERF_MASK_D_ACCESS_HITS_SHARED 0x0002 /* Hit Shared */
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#define XTPERF_MASK_D_ACCESS_HITS_EXCLUSIVE 0x0004 /* Hit Exclusive */
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#define XTPERF_MASK_D_ACCESS_HITS_MODIFIED 0x0008 /* Hit Modified */
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/*
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* XTPERF_CNT_MULTIPLE_LS selector mask
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*/
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#define XTPERF_MASK_MULTIPLE_LS_ALL 0x003F
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#define XTPERF_MASK_MULTIPLE_LS_0S_0L 0x0001 /* 0 stores and 0 loads */
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#define XTPERF_MASK_MULTIPLE_LS_0S_1L 0x0002 /* 0 stores and 1 loads */
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#define XTPERF_MASK_MULTIPLE_LS_1S_0L 0x0004 /* 1 stores and 0 loads */
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#define XTPERF_MASK_MULTIPLE_LS_1S_1L 0x0008 /* 1 stores and 1 loads */
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#define XTPERF_MASK_MULTIPLE_LS_0S_2L 0x0010 /* 0 stores and 2 loads */
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#define XTPERF_MASK_MULTIPLE_LS_2S_0L 0x0020 /* 2 stores and 0 loads */
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/*
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* XTPERF_CNT_OUTBOUND_PIF selector mask
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*/
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#define XTPERF_MASK_OUTBOUND_PIF_ALL 0x0003
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#define XTPERF_MASK_OUTBOUND_PIF_CASTOUT 0x0001 /* Castout */
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#define XTPERF_MASK_OUTBOUND_PIF_PREFETCH 0x0002 /* Prefetch */
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/*
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* XTPERF_CNT_INBOUND_PIF selector mask
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*/
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#define XTPERF_MASK_INBOUND_PIF_ALL 0x0003
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#define XTPERF_MASK_INBOUND_PIF_I_DMA 0x0001 /* Instruction DMA */
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#define XTPERF_MASK_INBOUND_PIF_D_DMA 0x0002 /* Data DMA */
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/*
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* XTPERF_CNT_PREFETCH selector mask
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*/
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#define XTPERF_MASK_PREFETCH_ALL 0x002F
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#define XTPERF_MASK_PREFETCH_I_HIT 0x0001 /* I prefetch-buffer-lookup hit */
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#define XTPERF_MASK_PREFETCH_D_HIT 0x0002 /* D prefetch-buffer-lookup hit */
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#define XTPERF_MASK_PREFETCH_I_MISS 0x0004 /* I prefetch-buffer-lookup miss */
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#define XTPERF_MASK_PREFETCH_D_MISS 0x0008 /* D prefetch-buffer-lookup miss */
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#define XTPERF_MASK_PREFETCH_D_L1_FILL 0x0020 /* Fill directly to DCache L1 */
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#endif /* __XT_PERF_CONSTS_H__ */
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