// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_CAN_STRUCT_H_
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#define _SOC_CAN_STRUCT_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* -------------------------- Register Definitions -------------------------- */
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/* The CAN peripheral's registers are 8bits, however the ESP32 can only access
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* peripheral registers every 32bits. Therefore each CAN register is mapped to
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* the least significant byte of every 32bits.
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*/
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typedef union {
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struct {
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uint32_t byte: 8; /* LSB */
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_reg_t;
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typedef union {
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struct {
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uint32_t reset: 1; /* MOD.0 Reset Mode */
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uint32_t listen_only: 1; /* MOD.1 Listen Only Mode */
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uint32_t self_test: 1; /* MOD.2 Self Test Mode */
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uint32_t acceptance_filter: 1; /* MOD.3 Acceptance Filter Mode */
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uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
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};
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uint32_t val;
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} can_mode_reg_t;
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typedef union {
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struct {
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uint32_t tx_req: 1; /* CMR.0 Transmission Request */
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uint32_t abort_tx: 1; /* CMR.1 Abort Transmission */
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uint32_t release_rx_buff: 1; /* CMR.2 Release Receive Buffer */
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uint32_t clear_data_overrun: 1; /* CMR.3 Clear Data Overrun */
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uint32_t self_rx_req: 1; /* CMR.4 Self Reception Request */
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uint32_t reserved27: 27; /* Internal Reserved */
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};
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uint32_t val;
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} can_cmd_reg_t;
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typedef union {
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struct {
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uint32_t rx_buff: 1; /* SR.0 Receive Buffer Status */
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uint32_t data_overrun: 1; /* SR.1 Data Overrun Status */
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uint32_t tx_buff: 1; /* SR.2 Transmit Buffer Status */
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uint32_t tx_complete: 1; /* SR.3 Transmission Complete Status */
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uint32_t rx: 1; /* SR.4 Receive Status */
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uint32_t tx: 1; /* SR.5 Transmit Status */
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uint32_t error: 1; /* SR.6 Error Status */
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uint32_t bus: 1; /* SR.7 Bus Status */
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_status_reg_t;
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typedef union {
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struct {
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uint32_t rx: 1; /* IR.0 Receive Interrupt */
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uint32_t tx: 1; /* IR.1 Transmit Interrupt */
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uint32_t err_warn: 1; /* IR.2 Error Interrupt */
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uint32_t data_overrun: 1; /* IR.3 Data Overrun Interrupt */
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uint32_t reserved1: 1; /* Internal Reserved (Wake-up not supported) */
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uint32_t err_passive: 1; /* IR.5 Error Passive Interrupt */
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uint32_t arb_lost: 1; /* IR.6 Arbitration Lost Interrupt */
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uint32_t bus_err: 1; /* IR.7 Bus Error Interrupt */
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_intr_reg_t;
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typedef union {
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struct {
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uint32_t rx: 1; /* IER.0 Receive Interrupt Enable */
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uint32_t tx: 1; /* IER.1 Transmit Interrupt Enable */
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uint32_t err_warn: 1; /* IER.2 Error Interrupt Enable */
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uint32_t data_overrun: 1; /* IER.3 Data Overrun Interrupt Enable */
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uint32_t reserved1: 1; /* Internal Reserved (Wake-up not supported) */
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uint32_t err_passive: 1; /* IER.5 Error Passive Interrupt Enable */
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uint32_t arb_lost: 1; /* IER.6 Arbitration Lost Interrupt Enable */
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uint32_t bus_err: 1; /* IER.7 Bus Error Interrupt Enable */
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_intr_en_reg_t;
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typedef union {
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struct {
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uint32_t baud_rate_prescaler: 6; /* BTR0[5:0] Baud Rate Prescaler */
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uint32_t sync_jump_width: 2; /* BTR0[7:6] Synchronization Jump Width*/
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_bus_tim_0_reg_t;
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typedef union {
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struct {
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uint32_t time_seg_1: 4; /* BTR1[3:0] Timing Segment 1 */
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uint32_t time_seg_2: 3; /* BTR1[6:4] Timing Segment 2 */
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uint32_t sampling: 1; /* BTR1.7 Sampling*/
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_bus_tim_1_reg_t;
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typedef union {
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struct {
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uint32_t arbitration_lost_capture: 5; /* ALC[4:0] Arbitration lost capture */
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uint32_t reserved27: 27; /* Internal Reserved */
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};
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uint32_t val;
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} can_arb_lost_cap_reg_t;
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typedef union {
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struct {
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uint32_t segment: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
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uint32_t direction: 1; /* ECC.5 Error Direction (TX/RX) */
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uint32_t error_code: 2; /* ECC[7:6] Error Code */
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_err_code_cap_reg_t;
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typedef struct {
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can_reg_t code_reg[4];
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can_reg_t mask_reg[4];
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uint32_t reserved32[5];
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} can_acc_filter_t;
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typedef union {
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struct {
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uint32_t rx_message_counter: 5; /* RMC[4:0] RX Message Counter */
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uint32_t reserved27: 27; /* Internal Reserved */
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};
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uint32_t val;
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} can_rx_msg_cnt_reg_t;
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typedef union {
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struct {
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uint32_t clock_divider: 3; /* CDR[2:0] CLKOUT frequency selector based of fOSC */
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uint32_t clock_off: 1; /* CDR.3 CLKOUT enable/disable */
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uint32_t reserved3: 3; /* Internal Reserved. RXINTEN and CBP not supported */
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uint32_t can_mode: 1; /* CDR.7 BasicCAN:0 PeliCAN:1 */
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uint32_t reserved24: 24; /* Internal Reserved */
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};
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uint32_t val;
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} can_clk_div_reg_t;
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/* ---------------------------- Register Layout ------------------------------ */
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typedef volatile struct {
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//Configuration and Control Registers
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can_mode_reg_t mode_reg; /* Address 0 */
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can_cmd_reg_t command_reg; /* Address 1 */
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can_status_reg_t status_reg; /* Address 2 */
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can_intr_reg_t interrupt_reg; /* Address 3 */
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can_intr_en_reg_t interrupt_enable_reg; /* Address 4 */
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uint32_t reserved_05; /* Address 5 */
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can_bus_tim_0_reg_t bus_timing_0_reg; /* Address 6 */
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can_bus_tim_1_reg_t bus_timing_1_reg; /* Address 7 */
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uint32_t reserved_08; /* Address 8 (Output control not supported) */
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uint32_t reserved_09; /* Address 9 (Test Register not supported) */
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uint32_t reserved_10; /* Address 10 */
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//Capture and Counter Registers
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can_arb_lost_cap_reg_t arbitration_lost_captue_reg; /* Address 11 */
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can_err_code_cap_reg_t error_code_capture_reg; /* Address 12 */
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can_reg_t error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */
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can_reg_t rx_error_counter_reg; /* RXERR[7:0] Receive Error Counter: Address 14 */
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can_reg_t tx_error_counter_reg; /* TXERR[7:0] Transmit Error Counter: Address 15 */
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//Shared Registers (TX Buff/RX Buff/Acc Filter)
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union {
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can_acc_filter_t acceptance_filter;
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can_reg_t tx_rx_buffer[13];
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}; /* Address 16-28 TX/RX Buffer and Acc Filter*/;
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//Misc Registers
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can_rx_msg_cnt_reg_t rx_message_counter_reg; /* Address 29 */
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can_reg_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */
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can_clk_div_reg_t clock_divider_reg; /* Address 31 */
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//Start of RX FIFO
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} can_dev_t;
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_Static_assert(sizeof(can_dev_t) == 128, "CAN registers should be 32 * 4 bytes");
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extern can_dev_t CAN;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC_CAN_STRUCT_H_ */
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