// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_GPIO_STRUCT_H_
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#define _SOC_GPIO_STRUCT_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct {
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uint32_t bt_select; /*NA*/
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uint32_t out; /*GPIO0~31 output value*/
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uint32_t out_w1ts; /*GPIO0~31 output value write 1 to set*/
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uint32_t out_w1tc; /*GPIO0~31 output value write 1 to clear*/
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union {
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struct {
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uint32_t data: 8; /*GPIO32~39 output value*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} out1;
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union {
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struct {
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uint32_t data: 8; /*GPIO32~39 output value write 1 to set*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} out1_w1ts;
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union {
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struct {
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uint32_t data: 8; /*GPIO32~39 output value write 1 to clear*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} out1_w1tc;
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union {
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struct {
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uint32_t sel: 8; /*SDIO PADS on/off control from outside*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} sdio_select;
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uint32_t enable; /*GPIO0~31 output enable*/
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uint32_t enable_w1ts; /*GPIO0~31 output enable write 1 to set*/
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uint32_t enable_w1tc; /*GPIO0~31 output enable write 1 to clear*/
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union {
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struct {
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uint32_t data: 8; /*GPIO32~39 output enable*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} enable1;
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union {
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struct {
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uint32_t data: 8; /*GPIO32~39 output enable write 1 to set*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} enable1_w1ts;
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union {
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struct {
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uint32_t data: 8; /*GPIO32~39 output enable write 1 to clear*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} enable1_w1tc;
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union {
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struct {
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uint32_t strapping: 16; /*GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel boot_sel_chip[5:0]} . Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3} . vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5} */
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uint32_t reserved16:16;
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};
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uint32_t val;
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} strap;
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uint32_t in; /*GPIO0~31 input value*/
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union {
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struct {
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uint32_t data: 8; /*GPIO32~39 input value*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} in1;
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uint32_t status; /*GPIO0~31 interrupt status*/
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uint32_t status_w1ts; /*GPIO0~31 interrupt status write 1 to set*/
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uint32_t status_w1tc; /*GPIO0~31 interrupt status write 1 to clear*/
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union {
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struct {
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uint32_t intr_st: 8; /*GPIO32~39 interrupt status*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} status1;
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union {
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struct {
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uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to set*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} status1_w1ts;
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union {
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struct {
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uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to clear*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} status1_w1tc;
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uint32_t reserved_5c;
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uint32_t acpu_int; /*GPIO0~31 APP CPU interrupt status*/
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uint32_t acpu_nmi_int; /*GPIO0~31 APP CPU non-maskable interrupt status*/
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uint32_t pcpu_int; /*GPIO0~31 PRO CPU interrupt status*/
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uint32_t pcpu_nmi_int; /*GPIO0~31 PRO CPU non-maskable interrupt status*/
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uint32_t cpusdio_int; /*SDIO's extent GPIO0~31 interrupt*/
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union {
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struct {
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uint32_t intr: 8; /*GPIO32~39 APP CPU interrupt status*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} acpu_int1;
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union {
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struct {
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uint32_t intr: 8; /*GPIO32~39 APP CPU non-maskable interrupt status*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} acpu_nmi_int1;
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union {
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struct {
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uint32_t intr: 8; /*GPIO32~39 PRO CPU interrupt status*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} pcpu_int1;
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union {
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struct {
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uint32_t intr: 8; /*GPIO32~39 PRO CPU non-maskable interrupt status*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} pcpu_nmi_int1;
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union {
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struct {
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uint32_t intr: 8; /*SDIO's extent GPIO32~39 interrupt*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} cpusdio_int1;
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union {
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struct {
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uint32_t reserved0: 2;
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uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/
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uint32_t reserved3: 4;
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uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
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uint32_t wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/
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uint32_t config: 2; /*NA*/
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uint32_t int_ena: 5; /*bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
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uint32_t reserved18: 14;
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};
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uint32_t val;
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} pin[40];
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union {
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struct {
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uint32_t rtc_max: 10;
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uint32_t reserved10: 21;
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uint32_t start: 1;
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};
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uint32_t val;
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} cali_conf;
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union {
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struct {
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uint32_t value_sync2: 20;
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uint32_t reserved20: 10;
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uint32_t rdy_real: 1;
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uint32_t rdy_sync2: 1;
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};
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uint32_t val;
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} cali_data;
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union {
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struct {
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uint32_t func_sel: 6; /*select one of the 256 inputs*/
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uint32_t sig_in_inv: 1; /*revert the value of the input if you want to revert please set the value to 1*/
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uint32_t sig_in_sel: 1; /*if the slow signal bypass the io matrix or not if you want setting the value to 1*/
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uint32_t reserved8: 24; /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1 if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/
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};
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uint32_t val;
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} func_in_sel_cfg[256];
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union {
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struct {
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uint32_t func_sel: 9; /*select one of the 256 output to 40 GPIO*/
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uint32_t inv_sel: 1; /*invert the output value if you want to revert the output value setting the value to 1*/
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uint32_t oen_sel: 1; /*weather using the logical oen signal or not using the value setting by the register*/
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uint32_t oen_inv_sel: 1; /*invert the output enable value if you want to revert the output enable value setting the value to 1*/
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uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/
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};
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uint32_t val;
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} func_out_sel_cfg[40];
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} gpio_dev_t;
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extern gpio_dev_t GPIO;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC_GPIO_STRUCT_H_ */
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