// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_HINF_REG_H_
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#define _SOC_HINF_REG_H_
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#include "soc.h"
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#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
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/* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */
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/*description: */
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#define HINF_DEVICE_ID_FN1 0x0000FFFF
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#define HINF_DEVICE_ID_FN1_M ((HINF_DEVICE_ID_FN1_V)<<(HINF_DEVICE_ID_FN1_S))
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#define HINF_DEVICE_ID_FN1_V 0xFFFF
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#define HINF_DEVICE_ID_FN1_S 16
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/* HINF_USER_ID_FN1 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
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/*description: */
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#define HINF_USER_ID_FN1 0x0000FFFF
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#define HINF_USER_ID_FN1_M ((HINF_USER_ID_FN1_V)<<(HINF_USER_ID_FN1_S))
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#define HINF_USER_ID_FN1_V 0xFFFF
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#define HINF_USER_ID_FN1_S 0
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#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
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/* HINF_SDIO20_CONF1 : R/W ;bitpos:[31:29] ;default: 3'h0 ; */
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/*description: */
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#define HINF_SDIO20_CONF1 0x00000007
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#define HINF_SDIO20_CONF1_M ((HINF_SDIO20_CONF1_V)<<(HINF_SDIO20_CONF1_S))
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#define HINF_SDIO20_CONF1_V 0x7
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#define HINF_SDIO20_CONF1_S 29
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/* HINF_FUNC2_EPS : RO ;bitpos:[28] ;default: 1'b0 ; */
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/*description: */
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#define HINF_FUNC2_EPS (BIT(28))
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#define HINF_FUNC2_EPS_M (BIT(28))
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#define HINF_FUNC2_EPS_V 0x1
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#define HINF_FUNC2_EPS_S 28
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/* HINF_SDIO_VER : R/W ;bitpos:[27:16] ;default: 12'h111 ; */
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/*description: */
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#define HINF_SDIO_VER 0x00000FFF
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#define HINF_SDIO_VER_M ((HINF_SDIO_VER_V)<<(HINF_SDIO_VER_S))
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#define HINF_SDIO_VER_V 0xFFF
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#define HINF_SDIO_VER_S 16
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/* HINF_SDIO20_CONF0 : R/W ;bitpos:[15:12] ;default: 4'b0 ; */
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/*description: */
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#define HINF_SDIO20_CONF0 0x0000000F
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#define HINF_SDIO20_CONF0_M ((HINF_SDIO20_CONF0_V)<<(HINF_SDIO20_CONF0_S))
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#define HINF_SDIO20_CONF0_V 0xF
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#define HINF_SDIO20_CONF0_S 12
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/* HINF_IOENABLE1 : RO ;bitpos:[11] ;default: 1'b0 ; */
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/*description: */
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#define HINF_IOENABLE1 (BIT(11))
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#define HINF_IOENABLE1_M (BIT(11))
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#define HINF_IOENABLE1_V 0x1
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#define HINF_IOENABLE1_S 11
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/* HINF_EMP : RO ;bitpos:[10] ;default: 1'b0 ; */
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/*description: */
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#define HINF_EMP (BIT(10))
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#define HINF_EMP_M (BIT(10))
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#define HINF_EMP_V 0x1
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#define HINF_EMP_S 10
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/* HINF_FUNC1_EPS : RO ;bitpos:[9] ;default: 1'b0 ; */
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/*description: */
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#define HINF_FUNC1_EPS (BIT(9))
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#define HINF_FUNC1_EPS_M (BIT(9))
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#define HINF_FUNC1_EPS_V 0x1
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#define HINF_FUNC1_EPS_S 9
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/* HINF_CD_DISABLE : RO ;bitpos:[8] ;default: 1'b0 ; */
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/*description: */
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#define HINF_CD_DISABLE (BIT(8))
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#define HINF_CD_DISABLE_M (BIT(8))
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#define HINF_CD_DISABLE_V 0x1
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#define HINF_CD_DISABLE_S 8
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/* HINF_IOENABLE2 : RO ;bitpos:[7] ;default: 1'b0 ; */
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/*description: */
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#define HINF_IOENABLE2 (BIT(7))
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#define HINF_IOENABLE2_M (BIT(7))
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#define HINF_IOENABLE2_V 0x1
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#define HINF_IOENABLE2_S 7
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/* HINF_SDIO_INT_MASK : R/W ;bitpos:[6] ;default: 1'b0 ; */
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/*description: */
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#define HINF_SDIO_INT_MASK (BIT(6))
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#define HINF_SDIO_INT_MASK_M (BIT(6))
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#define HINF_SDIO_INT_MASK_V 0x1
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#define HINF_SDIO_INT_MASK_S 6
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/* HINF_SDIO_IOREADY2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
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/*description: */
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#define HINF_SDIO_IOREADY2 (BIT(5))
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#define HINF_SDIO_IOREADY2_M (BIT(5))
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#define HINF_SDIO_IOREADY2_V 0x1
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#define HINF_SDIO_IOREADY2_S 5
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/* HINF_SDIO_CD_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */
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/*description: */
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#define HINF_SDIO_CD_ENABLE (BIT(4))
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#define HINF_SDIO_CD_ENABLE_M (BIT(4))
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#define HINF_SDIO_CD_ENABLE_V 0x1
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#define HINF_SDIO_CD_ENABLE_S 4
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/* HINF_HIGHSPEED_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */
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/*description: */
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#define HINF_HIGHSPEED_MODE (BIT(3))
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#define HINF_HIGHSPEED_MODE_M (BIT(3))
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#define HINF_HIGHSPEED_MODE_V 0x1
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#define HINF_HIGHSPEED_MODE_S 3
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/* HINF_HIGHSPEED_ENABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
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/*description: */
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#define HINF_HIGHSPEED_ENABLE (BIT(2))
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#define HINF_HIGHSPEED_ENABLE_M (BIT(2))
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#define HINF_HIGHSPEED_ENABLE_V 0x1
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#define HINF_HIGHSPEED_ENABLE_S 2
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/* HINF_SDIO_IOREADY1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: */
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#define HINF_SDIO_IOREADY1 (BIT(1))
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#define HINF_SDIO_IOREADY1_M (BIT(1))
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#define HINF_SDIO_IOREADY1_V 0x1
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#define HINF_SDIO_IOREADY1_S 1
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/* HINF_SDIO_ENABLE : R/W ;bitpos:[0] ;default: 1'b1 ; */
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/*description: */
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#define HINF_SDIO_ENABLE (BIT(0))
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#define HINF_SDIO_ENABLE_M (BIT(0))
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#define HINF_SDIO_ENABLE_V 0x1
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#define HINF_SDIO_ENABLE_S 0
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#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1C)
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/* HINF_SDIO_IOREADY0 : R/W ;bitpos:[17] ;default: 1'b1 ; */
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/*description: */
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#define HINF_SDIO_IOREADY0 (BIT(17))
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#define HINF_SDIO_IOREADY0_M (BIT(17))
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#define HINF_SDIO_IOREADY0_V 0x1
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#define HINF_SDIO_IOREADY0_S 17
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/* HINF_SDIO_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
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/*description: */
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#define HINF_SDIO_RST (BIT(16))
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#define HINF_SDIO_RST_M (BIT(16))
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#define HINF_SDIO_RST_V 0x1
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#define HINF_SDIO_RST_S 16
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/* HINF_CHIP_STATE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
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/*description: */
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#define HINF_CHIP_STATE 0x000000FF
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#define HINF_CHIP_STATE_M ((HINF_CHIP_STATE_V)<<(HINF_CHIP_STATE_S))
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#define HINF_CHIP_STATE_V 0xFF
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#define HINF_CHIP_STATE_S 8
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/* HINF_PIN_STATE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
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/*description: */
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#define HINF_PIN_STATE 0x000000FF
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#define HINF_PIN_STATE_M ((HINF_PIN_STATE_V)<<(HINF_PIN_STATE_S))
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#define HINF_PIN_STATE_V 0xFF
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#define HINF_PIN_STATE_S 0
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#define HINF_CIS_CONF0_REG (DR_REG_HINF_BASE + 0x20)
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/* HINF_CIS_CONF_W0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W0 0xFFFFFFFF
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#define HINF_CIS_CONF_W0_M ((HINF_CIS_CONF_W0_V)<<(HINF_CIS_CONF_W0_S))
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#define HINF_CIS_CONF_W0_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W0_S 0
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#define HINF_CIS_CONF1_REG (DR_REG_HINF_BASE + 0x24)
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/* HINF_CIS_CONF_W1 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W1 0xFFFFFFFF
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#define HINF_CIS_CONF_W1_M ((HINF_CIS_CONF_W1_V)<<(HINF_CIS_CONF_W1_S))
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#define HINF_CIS_CONF_W1_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W1_S 0
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#define HINF_CIS_CONF2_REG (DR_REG_HINF_BASE + 0x28)
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/* HINF_CIS_CONF_W2 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W2 0xFFFFFFFF
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#define HINF_CIS_CONF_W2_M ((HINF_CIS_CONF_W2_V)<<(HINF_CIS_CONF_W2_S))
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#define HINF_CIS_CONF_W2_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W2_S 0
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#define HINF_CIS_CONF3_REG (DR_REG_HINF_BASE + 0x2C)
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/* HINF_CIS_CONF_W3 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W3 0xFFFFFFFF
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#define HINF_CIS_CONF_W3_M ((HINF_CIS_CONF_W3_V)<<(HINF_CIS_CONF_W3_S))
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#define HINF_CIS_CONF_W3_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W3_S 0
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#define HINF_CIS_CONF4_REG (DR_REG_HINF_BASE + 0x30)
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/* HINF_CIS_CONF_W4 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W4 0xFFFFFFFF
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#define HINF_CIS_CONF_W4_M ((HINF_CIS_CONF_W4_V)<<(HINF_CIS_CONF_W4_S))
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#define HINF_CIS_CONF_W4_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W4_S 0
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#define HINF_CIS_CONF5_REG (DR_REG_HINF_BASE + 0x34)
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/* HINF_CIS_CONF_W5 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W5 0xFFFFFFFF
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#define HINF_CIS_CONF_W5_M ((HINF_CIS_CONF_W5_V)<<(HINF_CIS_CONF_W5_S))
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#define HINF_CIS_CONF_W5_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W5_S 0
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#define HINF_CIS_CONF6_REG (DR_REG_HINF_BASE + 0x38)
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/* HINF_CIS_CONF_W6 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W6 0xFFFFFFFF
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#define HINF_CIS_CONF_W6_M ((HINF_CIS_CONF_W6_V)<<(HINF_CIS_CONF_W6_S))
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#define HINF_CIS_CONF_W6_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W6_S 0
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#define HINF_CIS_CONF7_REG (DR_REG_HINF_BASE + 0x3C)
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/* HINF_CIS_CONF_W7 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
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/*description: */
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#define HINF_CIS_CONF_W7 0xFFFFFFFF
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#define HINF_CIS_CONF_W7_M ((HINF_CIS_CONF_W7_V)<<(HINF_CIS_CONF_W7_S))
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#define HINF_CIS_CONF_W7_V 0xFFFFFFFF
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#define HINF_CIS_CONF_W7_S 0
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#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
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/* HINF_DEVICE_ID_FN2 : R/W ;bitpos:[31:16] ;default: 16'h3333 ; */
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/*description: */
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#define HINF_DEVICE_ID_FN2 0x0000FFFF
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#define HINF_DEVICE_ID_FN2_M ((HINF_DEVICE_ID_FN2_V)<<(HINF_DEVICE_ID_FN2_S))
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#define HINF_DEVICE_ID_FN2_V 0xFFFF
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#define HINF_DEVICE_ID_FN2_S 16
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/* HINF_USER_ID_FN2 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
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/*description: */
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#define HINF_USER_ID_FN2 0x0000FFFF
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#define HINF_USER_ID_FN2_M ((HINF_USER_ID_FN2_V)<<(HINF_USER_ID_FN2_S))
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#define HINF_USER_ID_FN2_V 0xFFFF
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#define HINF_USER_ID_FN2_S 0
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#define HINF_DATE_REG (DR_REG_HINF_BASE + 0xFC)
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/* HINF_SDIO_DATE : R/W ;bitpos:[31:0] ;default: 32'h15030200 ; */
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/*description: */
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#define HINF_SDIO_DATE 0xFFFFFFFF
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#define HINF_SDIO_DATE_M ((HINF_SDIO_DATE_V)<<(HINF_SDIO_DATE_S))
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#define HINF_SDIO_DATE_V 0xFFFFFFFF
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#define HINF_SDIO_DATE_S 0
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#endif /*_SOC_HINF_REG_H_ */
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